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| 1 of 17 note: some revisions of this device may incorporate deviations from published specifications known as err ata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, cli ck here: www.maximintegrated.com/errata . 19 - 6719 ; rev 9/ 13 features ? integrated nv sram, real -time clock, crystal, power -fail control circuit, and lithium energy source ? clock registers are accessed identically to the static ram. these registers reside in the eight top ram locations. ? century byte reg ister ? totally nonvolatile with over 10 years of operation in the absence of power ? bcd -coded century, year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid through 2099 ? low - battery - voltage level indicator flag ? power - fail write protection allows for 10% v cc power -supply tolerance ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? dip module only standard jedec bytewide 8k x 8 static ram pinout ? powercap module board only surface - mountable package for direct connection to powercap containing battery and crystal replaceable battery (powercap) power - on reset output pin - for - pin compatible with other densities of ds174xp timekeeping ram ? underwriters laboratories (ul) recognized to prevent charging of the internal lithium battery pin configurations v cc we ce2 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n.c. a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28 - pin encapsulated pa ckage (28 pin 740) ds1743 1 n.c. 2 3 n.c. n.c. rst v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 n.c. n.c. 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 n.c. a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 n.c. x1 gnd v bat x2 34 - pin powercap module boar d (uses ds9034pcx+ or ds9034i -pcx+ powercap) ds1743p top view ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams downloaded from: http:///
ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 2 of 17 pin description pin name function pdip powercap 1 1, 2, 3, 31 C 34 n.c. no connection 2 30 a12 address input 3 25 a7 4 24 a6 5 23 a5 6 22 a4 7 21 a3 8 20 a2 9 19 a1 10 18 a0 11 16 dq0 data input/ output 12 15 dq1 13 14 dq2 14 17 gnd ground 15 13 dq3 data input/ output 16 12 dq4 17 11 dq5 18 10 dq6 19 9 dq7 pin name function pdip powercap 20 8 ce chip enable, active low 21 28 a10 add ress input 22 7 oe output enable, active low 23 29 a11 address input 24 27 a9 25 26 a8 26 ce2 chip enable 2 27 6 we write enable, active low 28 5 v cc power - supply input 4 rst power - on reset output, active low x1, x2 crystal connection v bat battery connection downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 3 of 17 ordering information part temp range pin - package voltage (v) top mark** ds1743 - 85+ 0c to +70c 28 edip module 5 ds1743 - 85 ds1743 - 100+ 0c to +70c 28 edip module 5 ds1743 - 100 ds1743 - 100 ind+ - 40c to +85c 28 edip module 5 ds1743 - 100 - ind ds1743p - 85+ 0c to +70c 34 powercap* 5 ds1743p - 85 ds1743p - 100+ 0c to +70c 34 powercap* 5 ds1743p - 100 ds1743p - 100ind+ - 40c to +85c 34 powercap* 5 ds1743p - 100 ind ds1743w - 120+ 0c to +70c 28 edip module 3.3 ds1743w - 120 ds1743w - 120 ind+ - 40c to +85c 28 edip module 3.3 ds1743w - 120 ind ds1743w - 150+ 0c to +70c 28 edip module 3.3 ds1743w - 150 ds1743w - 150 ind+ - 40c to +85c 28 edip module 3.3 ds1743w - 150 ind ds1743wp - 120+ 0c to +70c 34 powercap* 3.3 ds1743wp - 120 ds1743wp - 120 ind+ - 40c to +85c 34 powercap* 3.3 ds1743wp - 120 ind ds9034 pcx+ 0c to +70c powercap ds9034pc ds9034i - pcx+ - 40c to +85c powercap ind ds9034pci + denotes a lead(pb)- free /rohs-compliant package. * ds9034pcx+ or ds9034i- pcx+ required (must be ordered separately). **a + indicates lead (pb) -free. the top mark will include a + symbol on lead (pb) -free devices. description the ds1743 is a full - function, year -2000- compliant (y2kc), real - time clock/calendar (rtc) and 8k x 8 nonvolatile static ram. user access to all registers within the ds1743 is accomplished with a bytewide interface as shown in figure 1. the rtc information and control bits r eside in the eight uppermost ram locations. the rtc registers contain century, year, month, date, day, hours , minutes, and seconds data in 24- hour binary - coded decimal (bcd) format. corrections for the day of the month and leap year are made automatically. the rtc clock registers are double buffered to avoi d access of incorrect data th at can occur during clock update cycles. the double - buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. the ds1743 also contains its own power - fail circuitry, which deselects the device w hen the v cc supply is in an out -of- tolerance condition. when v cc is above v pf , the device is fully accessible. when v cc is below v pf , the internal ce signal is forced high, preventing any access. when v cc rises above v pf , access remains inhibited for t rec , allowing time for the system to stabilize. these features prevent loss of data from unpredicta ble system operation brought on by low v cc as errant access and update cycles are avoided. packages the ds1743 is available in two packages: the 28 - pin dip and the 34 - pin powercap module. the 28 - pin dip - style module integrates the crystal, lithium energy source, and silic on all in one package. the 34 -pin powercap module board is designed with contacts for connection to a se parate powercap (ds9034pcx) that contain s the crystal and battery. this design allows the powercap to be mounted on top of the ds1743p after the completion of the surface - mount process. mounting the powercap after the surface - mount process prevents damage to the crystal and battery due to the hi gh temperatures required for solder reflow. the powercap is keyed to prevent reverse insertion. the power cap module board and powercap are ordered separately and shipped in separate containers. downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 4 of 17 time and da te operation the time and date information is obtained by reading the appropriate r egister bytes. table 2 shows the rtc registers. the time and date are set or initialized by writin g the appropriate register bytes. the contents of the time and date registe rs are in the bcd format. the day -of- week register increments at midnight. values that correspond to the day of week are user - defined, but must be sequential (i.e., if 1 equals sunday, then 2 equals monday and so on). illogical time and date ent ries result in undefined operation. clock operations - reading the clock while the double - buffered register structure reduces the chance of reading incorrect data, internal updates to the ds1743 clock registers should be halted before clock data is r ead to prevent reading of data in transition. however, halting the internal clock register updating pro cess does not affect clock accuracy. updating is halted when a 1 is written into the read bit, bit 6 of t he century register (see table 2). as long as a 1 remains in that position, updating is halted. after a halt is issued, the registers reflect the count that is day, date, and time that was current at the moment the halt com mand was issued. however, the internal clock registers of the double - buffered system continue to up date so that the clock accuracy is not affected by the access of data. all the ds1743 registers are updated simulta neously after the internal clock register updating process has been re-enabled. updating is within a second after the read bit is written to 0. the read bit must be a zero for a minimum of 500 s to ensure the external registers are updated. downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 5 of 17 figure 1 . block diagram table 1 . truth table v cc ce ce2 oe we mode dq power v cc > v pf v ih x x x deselect high -z standby x v il x x deselect high -z standby v il v ih x v il write data in active v il v ih v il v ih read data out active v il v ih v ih v ih read high -z active v so < v cc < v pf x x x x deselect high -z cmos standby v cc ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 7 of 17 table 2 . register map address data function range b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1fff 10 year year year 00 C 99 1ffe x x x 10 month month month 01 C 12 1ffd x x 10 date date date 01 C 31 1ffc bf ft x x x day day 01 C 07 1ffb x x 10 hour hour hour 00 C 23 1ffa x 10 minutes minutes minutes 00 C 59 1ff9 osc 10 seconds seconds seconds 00 C 59 1ff8 w r 10 century century control 00 C 39 osc = stop bit r = read bit ft = frequency test w = write bit x = see note below bf = battery flag note: all indicated x bits must be set to 0 when written to ensure proper clock operation. retrieving data from ram or clock the ds1743 is in the read mode whenever oe (output enable) is low, we (w rite enable) is high, and ce (chip enable) is low. the device architecture allows ripple - through access to any of the address locations in the nv sram. valid data will be available at the dq pins within t aa after the last address input is stable, providin g that the, ce and oe access times and states are satisfied. if ce , or oe access times and states are not met, valid data will be available at the latter of chip enable access (t cea ) or at output enable access time (t cea ). the state of the data input/outpu t pins (dq) is controlled by ce and oe. if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while ce and oe remain valid, output data will remain valid for output data hol d time (t oh ) but will then go indeterminate until the next address access. downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 8 of 17 writing data to ram or clock the ds1743 is in the write mode whenever we , and ce are in their active state. the start of a write is referenced to the latter occurring transition of we , on ce . the addresses must be held valid throughout the cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another read or write cycle. data in must be valid t ds prior to the end of write and remain valid for t dh after ward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low the data bus can become active with read data defined by the address inputs. a low transition on we will then disable the outputs t wez after we goes active. data - retention mode the 5v device is fully accessible and data can be written or read o nly when v cc is greater than v pf. however, when v cc is below the power - fail point, v pf , (point at which write protection occurs) the internal clock registers and sram are blocked from any access. at t his time (powercap only) the power - fail reset -output signal ( rst ) is driven active and remains active until v cc returns to nominal levels. when v cc falls below the battery switch point v so (battery supply level), device power is switched from the v cc in to the backup battery. rtc operation and sram data are maintained f rom the battery until v cc is returned to nominal levels. the 3.3v device is fully accessible and data can be written or read on ly when v cc is greater than v pf . when v cc falls below the power - fail point, v pf , access to the device is inhibited. at this time the power - fail reset - output signal ( rst ) is driven active and remains active until v cc returns to nominal levels. if v pf is less than v so , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than v so , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v so . rtc operation and sram data are maintained from the battery unti l v cc is returned to nominal levels. the rst (powercap only) signal is an open - drain output and requires a pullup resistor. except fo r rst , all control, data, and address signals must be powered down when v cc is powered down. battery longevity the ds1743 has a lithium power source that is designed to provide energy f or clock activity and clock and ram data retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the ds1743 continuously for the life of the equipm ent in which it is installed. for specification purposes, the life expectancy is 10 years at +25 c with the internal cloc k oscillator running in the absence of v cc power. each ds1743 is shipped from dallas semiconductor with its lithi um energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery backup operation. actual life expectancy of the ds1743 will be longer than 10 years since no lithium battery energy is consumed when v cc is present. battery monitor the ds1743 constantly monitors the battery voltage of the internal batt ery. the battery flag bit (bit 7) of the day register is used to indicate the voltage level range of th e battery. this bit is not writeable and should always be a 1 when read. if a 0 is ever present, an exhausted l ithium energy source is indicated and both the contents of the rtc and ram are questionable. downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 9 of 17 absolute maximum ratings voltage range on any pin relative to ground - 0.3v to +6.0v storage temperature range .- 40c to +85c soldering temperature (edip) (leads, 10 seconds) ... +260c soldering temperature...see j -std- 020 specification (see note 8) this is a stress rating only and functional operation of the device at these or any other condi tions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended pe riods of time may affect device reliability. operating ran ge range temp range v cc commercial 0c to +70c 3.3v 10% or 5v 10% industrial - 40 c to +85 c 3.3v 10% or 5v 10% recommended dc operating conditions (t a = over the operating range.) parameter symbol conditions min typ max units notes logic 1 volta ge all inputs v ih v cc = 5v 10% 2.2 v cc +0.3v v 1 v cc = 3.3v 10% 2.0 v cc +0.3v v 1 logic 0 voltage all inputs v il v cc = 5v 10% - 0.3 +0.8 v 1 v cc = 3.3v 10% - 0.3 +0.6 v 1 dc electrical characteristics (5v) ( v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes active supply current i cc 15 50 ma 2, 3 ttl standby current ( ce = v ih , ce2 = v il ) i cc1 1 3 ma 2, 3 cmos standby current ( ce v cc - 0.2v; ce2 = gnd + 0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = - 1.0ma) v oh 2.4 1 output logic 0 voltage (i out = 2.1ma) v ol1 0.4 1 write - protection voltage v pf 4.20 4.50 v 1 battery switchover vo ltage v so v bat 1, 4 downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 10 of 17 dc electrical characteristics (3.3v) ( v cc = 3.3v 10% , t a = over the operating range.) parameter symbol min typ max units notes active supply current i cc 10 30 ma 2, 3 ttl standby current ( ce = v ih ) i cc1 0.7 2 ma 2, 3 cmos stan dby current ( ce v cc - 0.2v; ce2 = gnd + 0.2v) i cc2 0.7 2 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = - 1.0ma) v oh 2.4 1 output logic 0 voltage (i out =2.1ma) v ol1 0.4 1 write - protection voltage v pf 2.75 2.97 v 1 battery switchover voltage v so v bat or v pf v 1, 4 ac characteristics read cycle (5v) (v cc = 5.0v 10%, t a = over the operating range .) parameter symbol access units notes 70ns 85ns 100ns min max min max min max read cycle time t rc 70 85 100 ns address access time t aa 70 85 100 ns ce to ce2 to dq low -z t cel 5 5 5 ns 5 ce access time t cea 70 85 100 ns 5 ce2 access time t ce2a 80 95 105 ns 5 ce and ce2 data -off time t cez 25 30 35 ns oe to dq low -z t oel 5 5 5 ns oe access time t oea 35 45 55 ns oe data - off time t oez 25 30 35 ns output hold from address t oh 5 5 5 ns downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 11 of 17 ac characteristics read cycle (3.3v) ( v cc = 3.3v 10% , t a = over the operating range .) parameter symbol access units notes 120ns 150ns min max min max read cycle time t rc 120 150 ns address access time t aa 120 150 ns ce and ce2 low to dq low -z t cel 5 5 ns 5 ce access time t cea 120 150 ns 5 ce2 access time t ce2a 140 170 ns 5 ce and ce2 data - off time t cez 40 50 ns 5 oe low to dq low -z t oel 5 5 ns oe access time t oea 100 130 ns oe data - off time t oez 35 35 ns output hold from address t oh 5 5 ns read cycle timing diagram downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 12 of 17 ac charact eristics write cycle (5v) (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol access units notes 70ns 85ns 100ns min max min max min max write cycle time t wc 70 85 100 ns address setup time t as 0 0 0 ns 5 we pulse width t wew 50 65 70 ns ce pulse width t cew 60 70 75 ns 5 ce2 pulse width t ce2w 65 75 85 ns 5 data setup time t ds 30 35 40 ns 5 data hold time ce t dh 0 0 0 ns 5 data hold time ce2 t dh 8 8 8 ns 5 address hold time t ah 5 5 5 ns 5 we data - off time t wez 25 30 35 ns write recovery time t wr 10 10 10 ns ac characteristics write cycle (3.3v) ( v cc = 3.3v 10% , t a = over the operating range.) parameter symbol access units notes 120ns 150ns min max min max write cycle time t wc 120 150 ns address setup time t as 0 0 ns 5 we pulse width t wew 100 130 ns ce and ce2 pulse width t cew 110 140 ns 5 data setup time t ds 80 90 ns 5 data hold time ce t dh 0 0 ns 5 data hold time ce2 t dh 10 10 ns 5 address hold time t ah 0 0 ns 5 we data - off time t wez 40 50 ns write recovery time t wr 10 10 ns downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 13 of 17 write cycle timing write - enable controlled (see note 5) write cycle timing ce /ce2 - controlled ( see note 5) downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 14 of 17 p ower - up/down characteristics 5v (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes ce or we at v ih , ce2 at v il , before power - down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc fall time: v pf(min) to v so t fb 10 s v cc rise time: v pf(min) to v pf(max) t r 0 s power - up recover time t rec 35 ms expected data - retention time (oscillator on) t dr 10 years 6, 7 power - up/down timing (5v device) downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 15 of 17 power - up/down characteristics 3.3v ( v cc = 3.3v 10% , t a = over the operating range. ) parameter symbol min typ max units notes ce or we at v ih , before power - down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc rise time: v pf(min) to v pf(max) t r 0 s v pf to rst high t rec 35 ms expected data - retention time (oscillator on) t dr 10 years 6, 7 power - up/down waveform timing (3.3v device) capacitance (t a = +25 c) parameter symbol min typ max units notes capacitance on all input pins c in 7 pf capacitance on all output pins c o 10 pf downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 16 of 17 ac test conditions output load: 50 pf + 1ttl gate input pulse levels: 0 to 3.0v timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5ns notes: 1) voltages are referenced to ground. 2) typical values are at +25 c and nominal supplies. 3) outputs are open. 4) battery switchover occurs at the lower of either the battery termina l voltage or v pf . 5) the ce2 control signal functions the same as the ce signal except that the logic levels for active and inacti ve levels are opposite. if ce2 is used to terminate a write, the ce2 data hold tim e (t dh ) applies. 6) data - retention time is at +25 c. 7) each ds1743 has a built - in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined for dip modules as a cumulative time in the absence of v cc starting from the time power is first applied by the user. 8) rtc encapsulated dip modules (edip) can be successfully processe d through conventional wave - soldering techniques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post - solder cleaning with water - washing techniques is acceptable, provided that ultrasonic vibration is not used. see the powe rcap package drawing for details regarding the powercap package. package information for the latest package outline informati on and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. packa ge drawings may show a different suffix char acter, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 edip (740) mdf28+2 21-0245 34 pwrcp pc1+2 21-0246 downloaded from: http:/// ds1743/ds1743p y2k - compliant, nonvolatile timekeeping rams 17 of 17 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a m axim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to chan ge the circuitry and specifications without notice at a ny time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric value s quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1 - 408 - 601 - 1000 ? 201 3 maxim integrated products, inc. maxim integrated and the maxim integrated l ogo are trademarks of maxim integrated products, inc. revision history revision date description pages changed 9/13 updated the ordering information table; updated the setting the clock section add ed the parameter t ce2a for 3.3v read operation in the ac characteristics read cycle (3.3v) table 3, 4, 11 downloaded from: http:/// |
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